This invention relates to circuits and, in particular, to variable clock delay circuits.
Tapped delay lines may be used in clock generation circuits to provide an output clock signal whose phase can be varied with respect to an incoming reference signal. Tapped delay lines which are phase locked to a clock source essentially divide the period of the incoming reference signal into a predetermined number of time samples whereby these time samples can be utilized to vary the phase of the output clock signal. However, if an increase in resolution of the delay line is desired, more time samples are needed and, thus, the complexity of the delay line increases. For example, if the phase of the output clock signal is to be adjusted to a resolution of one-eighth of the period of the incoming reference signal, an eight tap delay line is required.
One attempt that prior art has made to generate different clock phases from an incoming reference signal is to replace the tap delay line with a phase locked-loop (PLL) circuit whereby a voltage controlled oscillator (VCO) of the PLL circuit includes a predetermined number of delay stages. By utilizing this method, if N delay stages of the VCO are used, then two times N (2N) clock phases of the incoming reference signal can be obtained via the rising and falling transitions occurring at each output of each of the N delay stages. However, this method only yields a 2-to-1 improvement and, thus, for high clock phase resolution, a large number of delay stages are still required.
Another attempt that prior art has made to vary the phase of an output clock signal with respect to an incoming reference signal is to multiply the frequency of the incoming reference signal of a PLL circuit by a predetermined factor thereby forcing the VCO of the PLL circuit to operate at a higher frequency than the incoming reference signal. The clock transitions of the higher frequency signal of the VCO are then utilized to provide clock phase adjustments. However, the phase resolution of the output clock signal is proportional to the predetermined factor. Thus, if a high resolution is desired, then a high predetermined factor is required thereby requiring the VCO to operate at a substantially high frequency.
Hence, there exists a need for an improved circuit that provides an output clock signal whose phase can be varied with respect to an incoming reference signal while minimizing the number of delay stages required.